The present invention relates to an electrically erasable and programmable nonvolatile semiconductor memory devices. More particularly, the present invention relates to a nonvolatile semiconductor memory device having NAND gate structured cells.
Recently, electrically erasable and programmable nonvolatile semiconductor memory devices (hereinafter referred to as an EEPROM) have become more highly integrated. In addition to increasing memory capacity, conventional EEPROMS operate at a lower power supply voltage. To obtain improved memory devices having large capacity and high density, the surface area allocated to peripheral circuits used to drive the memory device has been reduced. This is especially true for decoding circuits used to selectively drive memory cells. One technique used to reduce the number of peripheral circuit has resulted in an EEPROM having row block units, wherein each block shares a decoding circuit. U.S. Pat. No. 5,043,942 teaches one example of this particular technique. Specifically, the memory cell array is arranged in row block units, and each row block shares a control gate driving circuit in order to reduce the area occupied by the associated decoding circuit.
The reduced power supply voltage in the conventional EEPROM often causes difficulty in "reading" data from memory. In particular, the driving voltage applied to the to the word may become lower than the threshold voltage of the memory cell. In order to resolve this problem, the driving voltage must be sufficiently amplified such that it is higher than the memory cell threshold voltage.
FIG. 1 is a circuit diagram showing a portion of a conventional EEPROM having a block decoding circuit. In FIG. 1, a NAND cell string 10 is connected to a bit line and a ground voltage via first and second string selection transistors ST1 and ST2, respectively. Each NAND cell string includes eight memory cells M1 to M8 having their channels serially connected one to another and their gates respectively controlled by word lines WL1 to WL8. Each memory cell in the cell string is a conventional EEPROM cell having a control gate and a floating gate.
One row block comprises 256 NAND cell strings arranged in a row-wise direction and commonly controlled by the eight word lines. A block selection signal logic 11 receives externally provided block selection decoding information X, Y, and Z. The output of block selection signal logic 11 is commonly applied to first and second string selection logic 12 and 14. First string selection logic 12 includes a NAND gate receiving the block selection signal from block selection signal logic 11, and a string selection signal SD1. Second string selection logic 14 includes a NAND gate receiving the block selection signal from block selection signal logic 11 and a ground selection signal SS1.
The output of first string selection logic 12 is applied to one end of a string selection line SSL via the channel of a depletion type isolation transistor 18 having its gate connected to a control signal PRO. The output of the second string selection logic 14 is applied to a ground selection line GSL. The string selection line SSL is commonly connected to the gates of first string selection transistors ST1 of the NAND cell strings, thereby serving as a path for a control signal which either connects or isolates the NAND cell string to the bit line. The other end of the string selection line SSL is connected to an output node of a charge pump circuit 20 which outputs a boosting voltage, Vpp. When the string selection line SSL is charged to a logically high level (hereinafter referred to as a "high"), if a clock pulse OSC is applied, charge pump circuit 20 starts a charge pumping operation to raise string selection line SSL to Vpp.
Ground selection line GSL is commonly connected to the gates of the second string selection transistors ST2 of the respective NAND cell strings, thereby serving as a path for the control signal which operates to either connect or isolate the NAND cell string from ground. The control gate terminals of the memory cells in each NAND cell string are commonly connected to respective word lines WL1 to WL8 which, in turn, are connected to the control gate driving signals CG1 to CG8 via corresponding transfer transistors BT1 to BT8.
The gate terminals of transfer transistors BT1 to BT8 are commonly connected a pumping node N1. Pumping node N1 receives the output of first string selection logic 12 via an n-channel isolation transistor 16 having its gate controlled by Vcc, and being connected to the gate of a pump capacitor Cb to which control signal PUSH is applied. Accordingly, pump capacitor Cb operates to pump charge transferred from first string selection logic 12 to pumping node N1 via n-channel isolation transistor 16, thereby raising the potential of pumping node N1.
FIG. 2 is a waveform diagram illustrating a "read" operation for the EEPROM shown in FIG. 1. For the convenience of illustration, FIG. 2 shows, as an example, the reading operation for a first memory cell M1 in the first NAND cell string.
Before a block selection, i.e. before time t1, the output of block selection signal output logic 11 is placed at 0 volts, or a logically low level (hereinafter referred to as a "low"). The outputs of first and second string selection logic 12 and 14 are likewise low. At this time, control signal PUSH applied to pump capacitor Cb, control gate driving signals CG1 to CG8, string selection signal SD1, and ground selection signal SS1 all remain low. As node N1 is low, transfer transistors BT1 to BT8 are all turned OFF, and word lines WL1 to WL8 are allowed to float.
As the block is selected by the block selection decoding information X, Y, Z at time t1, the block selection signal output logic 11 outputs the block selection signal at a logical high, that is at the power supply voltage Vcc. Also at this time, control gate driving signal CG1 is applied at 0 volts, control gate driving signals CG2 to CG8 are applied at a voltage of Vcc, and string selection signal SD1 and ground selection signal SS1 are applied at a voltage of Vcc. As string selection signal SD1 and block selection signal are applied at a voltage of Vcc, the output voltage of first string selection logic 12 moves towards Vcc. Also at this time, a voltage Vcc-Vtn, where Vtn is the threshold voltage of n-channel isolation transistor 16, is applied to pumping node N1 and to the gates of transfer transistors BT1 to BT8. Word line WL1 corresponding to memory cell M1 receives a low voltage (0 volts) via the transfer transistor BT1 which has been turned ON, and the remaining word lines WL2 through WL8 receive a voltage of Vcc-2Vtn, obtained by subtracting the threshold voltage of the turned-ON transfer transistors BT2 to BT8 from the gate voltage thereof. When the gate of depletion type isolation transistor 18 receives a high voltage from control signal PRO, string selection line SSL and ground selection line GSL go to a voltage of Vcc.
When the read operation is started at time 12, control signal PUSH is applied at a voltage of Vcc level to boost pumping node N1, such that pumping node N1 is boosted to a voltage of Vcc+Vm+.alpha. by a charge pumping operation of capacitor Cb. The potential of boosted pumping node N1 is applied to the gates of transfer transistors BT1 to BT8, and word lines WL2 to WL8 are thereby charged to a voltage of Vcc which is the same voltage potential as control gate driving signals CG2 to CG8. Accordingly, memory cells M2 to M8 are turned ON and function as pass transistors, thereby reading out a threshold voltage from the memory cell M1 to bit line BL1. This threshold voltage indicates whether the stored read data of the memory cell M1 is "1" or "0."
Unfortunately, the conventional EEPROM shown in FIG. 1 is disadvantageous in that each memory block has a pump capacitor Cb. Thus, the area occupied by the memory block is larger than it might otherwise be, and a separate circuit is required to supply control signal PUSH to each pump capacitor. That is, the respective pump capacitors Cb are placed in the memory blocks in a one to one arrangement such that the voltage level boosted by the pump capacitors Cb will improve the driving capability of transfer transistors BT1 to BT8. However, this arrangement uses a great mount of surface area. In addition, since the control signal PUSH must be applied to each pump capacitor Cb, the resulting circuit structures further occupy surface area with peripheral circuits and, thus, lower memory device integration density. Finally, the foregoing problems may become more disadvantageous as memory devices continue to increase in capacity and to increase in the number of the memory blocks.